1. Field of the Invention
The present invention relates to the field of display, and in particular to a complementary metal-oxide-semiconductor (CMOS) gate driver an array (GOA) circuit.
2. The Related Arts
The gate driver on array (GOA) technology is the array substrate column drive technology, by using the thin film transistor (TFT) liquid crystal display (LCD) array processor to manufacture the gate scan driver circuit on the TFT array substrate to realize the column-by-column scan driving. The GOA technology has the advantages of low manufacture cost and the ability to realize narrow-border panels, and is used by many types of displays. GOA circuit has two basic functions: first, to output scan driving signal to drive the gate line in the panel to turn on the TFT in the display area so as to charge the pixels; and the second is the shift register; when the N-th scan driving signal is outputted, the clock control is used to perform outputting the (N+1)-th scan driving signal, and so on.
With the development of the low temperature poly-silicon (LTPS) semiconductor TFT, LTPS TFT liquid crystal display (LCD) attracts much attention. Because LTPS silicon crystal is more orderly arranged than non-crystal silicon, LTPS semiconductor shows a ultra-high carrier migration rate. The LCD utilizing LTPS TFT has the advantages of high resolution, rapid response, high luminance, and high opening ratio. Correspondingly, the integrated circuit (IC) around the panel of LTPS TFT LCD also becomes a focus of the display technology.
FIG. 1 is a schematic view showing a known CMOS GOA circuit, comprising a plurality of cascade GOA units, for a positive integer N, the N-th stage GOA unit comprising: an input and latch module 100, a signal processing module 300, and an output buffer module 400.
The input and latch module 100 is connected to a stage-propagated signal Q(N−1) of the previous stage GOA unit, a first clock signal CK1, and a first inverted clock signal XCK1, to obtain a stage-propagated signal Q(N) of the current stage based on the stage-propagated signal Q(N−1) of the previous stage GOA unit, the first clock signal CK1, and the first inverted clock signal XCK1, and then latches the stage-propagated signal Q(N) to input the propagated signal Q(N) to the signal processing module 300.
The signal processing module 300 receives the stage-propagated signal Q(N), a second clock signal CK2, a constant high level voltage VGH, a constant low level voltage VGL, and performs a NAND logic operation on the second clock signal CK2 and the stage-propagated signal Q(N) to generate a scan driver signal G(N) for the N-th stage GOA unit.
The output buffer module 400 is connected to the signal processing module 300, to increase the driving power of the scan driver signal G(N) and reduce the resistor-capacitor loading (RC loading) during the signal propagation.
Refer to FIG. 1 and FIG. 2. Before the GOA circuit in FIG. 1 starts normal operation, a voltage level reset process must be performed on the stage-propagated signal and scan driver signal. Therefore, each stage GOA unit of a known CMOS GOA circuit must also comprise a reset module 200. Take N-th stage GOA unit as an example. The reset module 200 comprises a P-type TFT, with the gate connected to a reset signal Reset, the source connected to the constant high level voltage VGH, and the drain connected to an input end of the inverter F in the input and latch module 100. When the reset signal Reset inputs a low level voltage, the P-type TFT becomes conductive and the inverter F performs inverting on the constant high level voltage VGH to pull down the voltage level of the stage-propagated signal Q(N), and then uses the low level stage-propagated signal Q(N) to make the scan driver signal G(N) become low level voltage. As such, the resetting of the stage-propagated signal Q(N) and the scan driver signal G(N) is realized. A STV signal is the circuit activation signal and a stage-propagated signal inputted to the first stage GOA unit. The STV is from the IC signal end.
The above know CMOS GOA circuit uses the clock signal and stage-propagated signal Q(N) to perform logic gate control, and the signal processing module 300 generates the scan driver signal G(N) for N-th stage GOA unit. The clock signal is from the IC, and will experience a large RC delay during the propagation to cause the deformation of the clock signal. As shown in FIG. 2, the delay of the clock signal will cause the delay of the output from the signal processing module 300, leading to affecting the output of the scan driver signal G(N) to cause a larger RC delay for scan driver signal G(N). When driving high resolution panels, a larger RC delay will cause abnormal display of the panels.